The present invention relates to a semiconductor memory and, more particularly, to a programmable read-only memory (PROM) into which data can be written.
A floating-gate, n-channel MOS transistor used as a memory cell in a programmable read-only memory (PROM) has the structure as shown in FIG. 1. As is illustrated in this figure, source 12 and drain 13, both constituted by N.sup.+ diffusion layers, are formed in one major surface region of P-type silicon substrate 11. Insulation film 14 is formed on the major surface of substrate 11. Floating gate 15 is embedded in insulation film 14 and is located above that portion of substrate 11 which is situated between source 12 and drain 13. Floating gate 15 thus floats electrically above substrate 11. Control gate 16 is formed on insulation film 14 and is located above floating gate 15. Source electrode 17 is formed in one of two contact holes cut in insulation film 14, and is thereby electrically connected to source 12. Drain electrode 18 is formed in the other contact hole, and is thereby electrically connected to drain 13.
Now, it will be explained how data "0" is written into the n-channel MOS transistor shown in FIG. 1.
First, P-type silicon substrate 11 and source 12 are set at the ground potential (GND). Then, a voltage of, for example, 12.5 V is applied to control gate 16, and a voltage of, for example, 7.0 V is applied to drain 13. As a result, the potential of floating gate 15 rises to, for instance, 9.0 V, since 12.5 V has been applied to control gate 16. Hence, 9.0 V is applied between floating gate 15 and substrate 11, whereby an inversion layer, that is, N-type layer 19, is formed in that surface region of substrate 11 which separates source 12 and drain 13. The electrons within inversion layer 19 are moved toward drain 13 by the voltage applied to drain 13, and collide with those silicon atoms of substrate 11 which are present near drain 13. A so-called "electron avalanche" occurs near drain 13, thereby generating new electrons. Some of these electrons drift to drain 13, and the rest are injected into floating gate 15.
As more and more electrons accumulate in floating gate 15, the potential of the gate falls. When the potential falls to a specific value, electrons can no longer be injected into gate 15. At this point, the writing of data "0" is completed.
With the large memory capacity PROM comprising a number of memory cells having the structure as shown in FIG. 1, it is generally required that data be written into each memory cell in the shortest time possible; for example, within 1 millisecond, or within 100 microseconds.
FIG. 2 shows a circuit consisting of one memory cell 21 of the type shown in FIG. 1, and a circuit for writing data thereinto. Also provided are n-channel MOS transistors 22 and 23, having their current paths connected in series. MOS transistor 22, which is a data-writing transistor, has its drain connected to high-voltage power supply Vpp for supplying 12.5 V, and its gate receives a write signal. MOS transistor 23 is a column-selecting transistor, and its gate receives a column-address signal of voltage Vpp. A row-address signal of voltage Vpp is applied to the control gate of memory cell 21.
When the voltage of the column-address signal and that of the row-address signal both rise to 12.5 V and the drain voltage of memory cell 21 rises to about 7 V, electrons are injected from the substrate into the floating gate of memory cell 21, and data "0" is thereby written into memory cell 21.
FIG. 3 is a graph illustrating the data-writing characteristic of the semiconductor memory circuit shown in FIG. 2. In this figure, curve I indicates the operation characteristic, i.e., the relationship between the drain current Ids and drain voltage Vds which memory cell 21 exhibits when a voltage of 12.5 V (i.e., voltage Vpp) is applied to its control gate. As curve I reveals, the electron avalanche occurs in memory cell 21, at point T. Curve II represents the way in which the load applied to memory cell 21 changes as current Ids and voltage Vds change. Intersection P of curves I and II denotes the operation point of memory cell 21. Curve II is specific to a load constituted by an n-channel MOS transistor.
Data can be written into memory cell 21 even if current Ids is below point T, provided the data does not have to be written at high speed. In order that data can be written in at a sufficiently high speed, drain current Ids should be at the same level as, or above, point T.
However, the angle defined by curves I and II is small in the region above point T, with the result that, in this region, drain current Ids varies considerably even if the inclination of curve I varies only a little, thus causing the data-writing speed of memory cell 21 to vary considerably. The inclination of curve I depends on the process parameters of cell 21, such as the size of the transistor, the impurity concentration of the substrate, the threshold voltage of the transistor, and the like. Since each of the process parameters varies from one memory cell to another, the memory cells in the PROM therefore cannot have the same curve I, i.e., the same data-writing characteristic. Hence, in the conventional PROM, the data-writing current varies considerably from one memory cell to another, with the result that the data-writing characteristic of each cell is unstable.
Most programmable read-only memories (PROMs) have the structure shown in FIG. 4. As is illustrated in this figure, a PROM has memory-cell matrix 31, which comprises a floating-gate, and n-channel MOS transistors 32.sub.ll to 32.sub.mn which are used as memory cells. The MOS transistors are arranged in rows and columns. The control gates of the n-channel MOS transistors forming each row are coupled to a row-signal line. More specifically, MOS transistors 32.sub.1l to 21.sub.1n of the first row have their control gates connected to the first row-signal line 33.sub.1, MOS transistors 32.sub.2l to 32.sub.2n of the second row have their control gates coupled to the second row line 33.sub.2, and so forth. MOS transistors 32.sub.ml to 32.sub.mn of the last row have their control gates coupled to the last row-signal line 33.sub.m. Further, the drains of the MOS transistors forming each column are coupled to a column-signal line. More precisely, MOS transistors 32.sub.l1 to 32.sub.m1 of the first column have their drains connected to the first column-signal line 34.sub.l, MOS transistors 32.sub.l2 to 32.sub.m2 of the second column have their drains coupled to the second column-signal line 34.sub.2, and so forth. MOS transistors 21.sub.ln to 32.sub.mn of the last column have their drains connected to the last column-signal line 34.sub.n. The sources of all n-channel MOS transistors 32.sub.ll to 32.sub.mn are connected to the ground.
The PROM further comprises row decoder 35 and column-selecting circuit 36. The output of row decoder 35 is coupled to row-signal lines 33.sub.l to 33.sub.m . The column-selecting circuit 36 is connected to column-signal lines 34.sub.l to 34.sub.n. Column-selecting circuit 36 comprises column-selecting n-channel MOS transistors 37.sub.l to 37.sub.n, which are turned on and off by outputs A.sub.l to A.sub.n of a column decoder (not shown). MOS transistors 37.sub.l to 37.sub.n are connected at one end to column-signal lines 34.sub.l to 34.sub.n, respectively, and at the other end to one another, thus forming a node. Data-reading n-channel MOS transistor 38 and data-writing MOS transistor 39 are each connected at one end to this node. The other end of MOS transistor 38 is connected to the input terminal of sense amplifier circuit 40 and also to resistor 41, which in turn is coupled to power supply potential Vcc. Data-reading MOS transistor 38 is turned on by a read-mode signal. The other end of data-writing MOS transistor 39 is coupled to high-voltage power supply potential Vpp. MOS transistor 39 is turned on by the output of data-writing gate circuit 42. Gate circuit 42 comprises buffer circuit 43 and AND gate 44. Buffer circuit 43 is coupled to power supply potential Vpp, and has an output terminal connected to the gate of data-writing MOS transistor 39. AND gate 44 has an output terminal coupled to the input terminal of buffer circuit 43, and provides a logical sum of a write-mode signal and data Din to be written in the PROM.
The operation of the conventional PROM shown in FIG. 4 will now be described.
Assume that memory cell 32.sub.ij (i=1 to m, j=1 to n) is selected by outputs of row decoder 35 and the column decoder (not shown). Also assume that the read-mode signal and the write-mode signal are at level "1" and level "0",respectively, and, thus, MOS transistor 38 is on, and MOS transistor 39 is off. In this state, sense amplifier circuit 40 detects the data stored in memory cell 32.sub.ij. This data, Dout, appears at the output terminal of sense amplifier circuit 40.
Data "0" and data "1" can be written into any desired memory cell. When the write-mode signal and the read-mode signal are at level "1" and level "0", respectively, MOS transistor 38 is off. When data Din is "1", the output of AND gate is at level "1". As a result, MOS transistor 39 is on. A high voltage is therefore applied from high-voltage power supply Vpp to column-signal line 34.sub.j, via MOS transistor 39 and column-selecting MOS transistor 37.sub.j (j=1 to n), which has been selected by the column decoder. Hence, data "0" is written into memory cell 32.sub.ij coupled to row-signal line 33.sub.i selected by row decoder 35, and to column-signal line 34.sub.j connected to column-selecting MOS transistor 37.sub.j. On the other hand, when data Din is "0" while the write-mode signal and the read-mode signal remain at level "1" and level "0", respectively, the output of AND gate 44 is at level "0". MOS transistor 39 is therefore off. In this case, no high voltage is applied to memory cell 32.sub.ij selected by row decoder 35 and the column decoder. Hence, data "1" is written into memory cell 32.sub.ij.
FIG. 5 shows memory cell 32.sub.ij and the circuit for writing data thereinto. In order to write data "0" into memory cell 32.sub.ij, the gate potentials of data-writing MOS transistor 39, column-selecting MOS transistor 37.sub.j, and memory cell 32.sub.ij are set at Vpp level (usually 12.5 V), thereby turning these MOS transistors on. Current Iw flows from high-voltage power source Vpp, coupled to the drain of MOS transistor 39, to the source (i.e., ground GND) of floating-gate MOS transistor 32.sub.ij used as memory cell 32.sub.ij. The hot carriers (i.e., electrons) induced by current I are injected into the floating gate of memory cell 32.sub.ij, thereby writing data "0" thereinto. In order to write data "1" into memory cell 32.sub.ij, the gate potential of data-writing MOS transistor 39 is set at the GND level. Although the potentials at the control gates of column-selecting MOS transistor 37.sub.j and memory cell 32.sub.ij are both at the Vpp level, MOS transistor 39 is off. Hence, no current flows to memory cell 32.sub.ij from high-voltage power source Vpp. As a result, no electrons are injected into the floating gate of memory cell 32.sub.ij, and this memory cell stores data "1".
As has been described above, memory cell 32.sub.ij is an n-channel MOS transistor. Column-selecting MOS transistor 37.sub.j and data-writing MOS transistor 39 are also n-channel transistors.
FIG. 6 is a circuit diagram modified from the diagram of FIG. 5, and explains how data "0" is written into memory cell 32.sub.ij. When high voltage Vpp is applied to the gate and also to the drain of transistor 39, this transistor is thus on. In this condition, the source potential Va of MOS transistor 39 has not reached the Vpp level. Source potential Va is given as follows, provided that MOS transistor 39 is of enhancement type: EQU Va.ltoreq.Vpp-V.sub.THN
where V.sub.THN is the threshold voltage of MOS transistor 39. Source potential Va is not equal to the substrate voltage (GND), and hence, due to the back-gate bias effect, the apparent threshold voltage of MOS transistor 39 rises, and source potential Va is therefore lower than Vpp-V.sub.THN. Further, the source potential Vb of column-selecting MOS transistor 37.sub.j is approximately equal to source potential Va of MOS transistor 39. It follows that potential Va is applied to the source of memory cell 32.sub.ij. As long as the Vpp level is sufficiently high, source potential Va of MOS transistor 39 is also high, and there is no problem in programming the PROM.
However, the recent trend has been for the power-supply voltage level Vpp to be lowered. This is because an LSI will deteriorate rapidly when a high voltage is applied to the signal lines incorporated therein. In the case of a CMOS-LSI, the high voltage applied to the signal lines causes a latch-up phenomenon to occur.
Even when power-supply voltage level Vpp is lowered, it is necessary, in order to write data into memory cell 32.sub.ij, to supply a current large enough to generate hot carriers between the source and drain of memory cell 32.sub.ij. In order to supply such a large current, source potential Vb of column-selecting MOS transistor 37.sub.j must also be raised to as close to the Vpp level as possible. Nevertheless, source potential Vb is inevitably lowered by the threshold voltage V.sub.THN of data-writing MOS transistor 39, and hence, when power-supply voltage level Vpp is lowered, the current flowing through the source-drain path of memory cell 32.sub.ij decreases considerably, thus reducing the speed of writing data "0" into memory cell 32.sub.ij.
As has been described above, in the conventional PROM, the data-writing voltage is lowered by the threshold voltage of the data-writing MOS transistor. The current flowing through the source-drain path of each memory cell therefore decreases. Consequently, the efficiency of writing data "0" into the memory cell is inevitably low.